Welcome to the home of Microelectronics and VLSI. Research interests of faculty members includes Spintronics, Semiconductor Device Modeling and Simulation, Solid State Devices, Organic Electronics, Transparent Semiconductors and Photovoltaic systems, VLSI technology including analog/mixed signal circuit design, VLSI Circuit Design and RFID Tag Chip Design.
The department has excellent research laboratories and support facilities in the area of Microelectronics and VLSI. Micro fabrication lab with basic semiconductor processing capability for silicon as well as organic material based devices (OLED, organic solar cells, OTFT, etc.), Solar cell characterization lab, photo mask making facility, Semiconductor device lab with capability to synthesize organic materials for organic LEDs and solar cells, Integrated circuits simulation and VLSI design laboratory with all the modern EDA tools, (e.g. CADENCE, SYNOPSYS, Mentor Graphics, MAGMA, COWARE, XILINX based gate array design & programming tools, etc.) and adequate hardware in the form of servers and good number of workstations for research and course work. Three teaching/training labs have been developed to train students in areas related to organic electronics. These are the organic electronics processing lab, the organic electronics characterization lab and the organic electronics simulation lab.
The Semiconductor Device Fabrication Lab is engaged in the research and technology development of silicon and organic based materials and devices. The fabrication and characterization of transistors, diodes, photo-diode, solar cells, OLEDs, TFTs and similar devices can be carried out in the Lab. The basic materials are also developed.
- Organic Electronics.
- Organic Solar Cells.
- Organic Thin Film Transistors.
- Organic Light Emitting Diodes
- MBRAUN Glove box with spinner and evaporator
- Hind Hinvac vacuum thermal deposition system
- Furnaces for silicon wafer oxidation and doping
- Class 1000 Clean room
- Solar Simulator
- Spectral Response
- "Solar Photovoltaic Energy Harnessing", S. Sundar Kumar Iyer, Review Article in Proceedings of the Indian National Science Academy, Volume 81, No. 4, September 2015 pp. 1001-1021
- "Increase in hole mobility in poly (3-hexylthiophene-2,5-diyl) films annealed under electric field during the solvent drying step", Anirban Baguia, S. Sundar Kumar Iyer, Organic Electronics, Volume 15, Issue 7, July 2014, Pages 1387–1395
- "Static electric field enhanced recrystallization of copper phthalocyanine thin film during annealing", Anukul Prasad Parhia and S.Sundar Kumar Iyer, Journal of Crystal Growth, Volume 380, 1 October 2013, Pages 123–129
- "Effect of metal nanoparticles' contact angle on absorption of light in organic solar cell active layer", Devika Kataria and S. Sundar Kumar Iyer, Journal of Renewable Sustainable Energy, Volume 5, Issue 3, June 2013, 031617.
- Study of electrodes in organic solar cell for efficiency and relialbility improvement.
- Design and Development of Organic Solar Cell Sub-Modules, One of the participating lab in "Centre for excellence for Large Area Flexible Electronics" at IIT Kanpur.
- S. Sundar Kumar Iyer
- Baquer Mazhari
- Sandeep Kumar
- Sayed Mazahir Hussain Rizvi
- Rajesh Agarwal
- Chinmay Nitin Oak
- Patiram
- S Sundar Kumar Iyer
x-7820 This email address is being protected from spambots. You need JavaScript enabled to view it. - Mr. Patiram
x-7832 This email address is being protected from spambots. You need JavaScript enabled to view it.
The VLSI-EDA lab is equipped with the most up-to-date industry standard VLSI EDA tools and hardware resources. The lab facility includes course lab for course projects and assignments, research lab for thesis and research and testing lab for VLSI testing. The server room in VLSI Lab houses over 15 servers which power all the Linux and Windows workstations in course, research and testing sections. The lab also has an in-house library holding of around 60 books related to VLSI and allied fields for student reference.
- State-of-art facility for research and teaching at postgraduate level.
- Software tools: Synopsys, Cadence, Mentor Graphics, Xilinx, Keysight ADS, Keysight IC-Cap, Synopsys Advanced TCAD, Silvaco TCAD 3D, Silvaco AMS, GTS TCAD Framework and QuantumWise ATK.
- Open Source Tools: OOMMF, QCADesigner, Spice3f5, BSIM4 and QuantumEspresso.
- Extended-use Off-maintenance tools: Silvaco TCAD 2D, Tanner EDA, MEMS and AimSpice.
- FPGA prototyping boards, Analog and Digital IO boards and DSP kits from Xilinx.
- Function Generators, Oscilloscopes and Logic Analyzers.
- Networked computing environment with Linux and Windows.
The course projects have been designed in analog, digital and rf areas using software and hardware tools.
PG:
- EE610: Analog/ Digital VlSI Circuits
- EE614: Solid State Devices - l
- EE616: Semiconductor Device Modelling
- EE618: Integrated Circuit Technology
- EE619: VLSI System Design
- EE645: Monolithic Microwave ICs
- EE681: Compact Modeling
- EE698I: Solar Photovaltaic Technology
UG:
- EE370: Digital Electronics and Microprocessor Technology
- EE413: Semiconductor Devices Technology
- Organic Thin Film Transistor
- Silicon-On-Insulator MOSFET
- VLSI Interconnections
- Carbon Nanotubes
- Hetero-Junction Bipolar Transistor
- Novel Semiconductor Devices
- Tunnelling FET
- Junction-less FET
- Ultra-Thin Body Silicon-On-Insulator
- Digital ASIC Design
- Full Custom ASIC Design
- Advanced CMOS Devices
- High Electron Mobility Transistors
- Compact Modelling
- MOSFET Modelling
- Device Simulation
- Physics of 2D Materials applications
- Prof. Aloke Dutta (EE)
- Prof. B. Mazhari (EE)
- Prof. S. S. K. Iyer (EE)
- Dr. Y. S. Chauhan (EE)
- Prof. Animesh Biswas (EE)
- Prof. A.R. Harish (EE)
- Dr. Jaleel Akhtar (EE)
- Prof. Rajat Moona (CSE) On-Leave
- Prof. Ajay Jain (CSE)
- Prof. Sandeep Shukla (CSE)
- Prof. Shashank Mehta (CSE)
- Dr. Mainak Chaudhuri (CSE) Co-CI, SMDP-C2SD
- Prof. Deepak Gupta (MSE)
- Prof. Monika Katiyar (MSE)
- Prof. Ashish Garg (MSE)
- Dr. Sarang Ingole (MSE)
- Prof. Y.N. Mohapatra (MSP)
- Prof. R. S. Ashwin Kumar (EE)
- Prof. Imon Mondal (EE)
- Prof. Chithra (EE)
- Mr. Bharat Somaiya, Senior Technician & Sys-Admin
- Dr. Chandra Shekhar Gautam (EE)
- Dr. Mohamed Asan Basiri M (CSE)
- Dr. Sarvesh Singh Chauhan (EE)
- Dr. Sudip Ghosh (EE)
- Dr. Tapas Dutta (EE)
- Mr. Basanagauda B. Patil (SCDT)
- Mr. Gavax Joshi (EE)
- Mr. Ragavendra Dangi (EE)
- Mr. Sanjay Sharma (EE)
- Mr. Uttam Kumar Das (EE)
- Mr. Amol Domaji Gaidhane (EE)
- Mr. Ashish K. Agrawal (EE)
- Mr. Avirup Dasgupta (EE)
- Mr. Ball Mukund Tripathi (EE)
- Mr. Chandan Yadav (EE)
- Mr. Chetan Gupta (EE)
- Mr. Dabhi Chetankumar Trikambhai (EE)
- Mr. Dharmander Malik (EE)
- Mr. Dinesh R (EE)
- Mr. Girish Pahwa (EE)
- Mr. Prateek Jain (EE)
- Mr. Priyank Rastogi (EE)
- Ms. Rajani Bisht (EE)
- Mr. Rajesh Agrawal (EE)
- Mr. Ravi Goel (EE)
- Ms. Sandhya Chandravanshi (MSP)
- Mr. Satya Gopal Dinda (EE)
- Mr. Shantanu Agnihotri (EE)
- Mr. Sheikh Aamir Ahsan (EE)
- Mr. Shiromani B. Rahi (EE)
- Ms. Shruti Mehrotra (EE)
- Mr. Sona Das (EE)
- Ms. Tannu Gupta (EE)
- Mr. Tapendu Mandal (MSE)
- Prof. R. S. Ashwin Kumar
E-mail: This email address is being protected from spambots. You need JavaScript enabled to view it.
Phone: +91-512-259-2165
Location: WL-120 - Prof. Imon Mondal
E-mail: This email address is being protected from spambots. You need JavaScript enabled to view it.
Phone: +91-512-259-7732 | +91-512-259-0063
Location: WL-211 - Prof. Chithra
E-mail: This email address is being protected from spambots. You need JavaScript enabled to view it.
Phone: +91-512-259-2199
Location: WL-211 - Mr. Bharat Somaiya
E-mail: This email address is being protected from spambots. You need JavaScript enabled to view it.
Location: ACES-114
- Organic Electronics.
- Organic Solar Cells.
- Organic Thin Film Transistors.
- Organic Light Emitting Diodes.
- Thermal Evaporator
- Spin Coater `
- Ultrasonicator
- Characterization Setup
- Traps signature in steady state current-voltage characteristics of organic diode, Rizvi, S. M. H. and Mantri, P. and Mazhari, B., Journal of Applied Physics, 115, 244502 (2014)
- Prachi Mantri, S.M.H. Rizvi, B. Mazhari, Estimation of built-in voltage from steady-state current-voltage characteristics of organic diodes, Organic Electronics, Volume 14, Issue 3, August 2013, Pages 2034-2038.
- Vinay Kumar Singh and Baquer Mazhari, Measurement of threshold voltage in organic thin film transistors, Appl. Phys. Lett. 102, 253304, June 2013.
- Arun Tej Mallajosyula, S. Sundar Kumar Iyer, Baquer Mazhari, Charge transport in polythiophene: fullerene: nanotube bulk heterojunction photovoltaic devices investigated by impedance spectroscopy, Current Applied Physics, June 2013
- M. N. Islam and B. Mazhari, Organic Thin Film Transistors with Asymmetrically Placed Source and Drain Contact, Organic Electronics, Volume 14, Issue 3, March 2013, Pages 862-867.
- Ashish K. Agarwal, and B. Mazhari, Simultaneous Extraction of Source and Drain Resistances in Top Contact Organic Thin Film Transistors From a Single Test Structure, Organic Electronics: physics, materials, applications 13 (11) , pp. 2659-2666, Nov. 2012.
- Mallajosyula, Arun Tej, Iyer, S. Sundar Kumar; Mazhari Baquer, Capacitance-voltage characteristics of P3HT:PCBM bulk heterojunction solar cells with ohmic contacts and the impact of single walled carbon nanotubes on them, Org. Electronics, Volume 13, Issue 7, July 2012, Pages 1158-1165.
- Vinay K. Singh, Baquer Mazhari, Impact of scaling of dielectric thickness on mobility in top-contact pentacene organic thin film transistors , J. Appl. Phys. 111, 034905 , Feb 2012
- Vinay K. Singh, Ashish K. Agarwal and Baquer Mazhari, Measurement of Source Resistance in Top Contact Organic Thin Film Transistors, IEEE Electron Device Lett., EDL-9, March 2012
- Vinay K. Singh, Baquer Mazhari, Accurate characterization of organic thin film transistors in the presence of gate leakage current, AIP ADVANCES 1, 042123 (2011)
- Dr B Mazhari
- Dr SSK Iyer
- Rajesh Agarwal
- Syed Rizvi
- Nadeem Firoz
- Peeyush
- Nama Jain
- Saurabh
- Anubhav
- Pankaj
- Abhinay
- Shobhojit
- Patiram
- Dr B Mazhari
- Dr SSK Iyer
Location: WL 118
Lab Contact No:7189
- 200mm wafer characterization facility: DC, CV and RF characterization of electron devices, for temperature range -65C to 200C.
- Equipped with state of the art software tools:
- SPICE simulators - HSPICE, SPECTRE, ADS
- RF simulation and design - Agilent ADS and Microwave office
- TCAD Simulators - Silvaco Atlas and Synopsys Sentaurus
- Parameter Extraction tool - ICCAP
- Atomistic Simulator - ATK Quantumwise, NanoMOS, NextNano
- Multiprocessor Linux servers and workstations
- Library with reference books and manuals along with projector, screen,whiteboard for discussions and group meetings
- Network Printing, Scanning and Xeroxing
- P. Kushwaha, H. Agarwal, S. Khandelwal, J. P. Duarte, A. Medury, C. Hu and Y. S. Chauhan, "BSIM-IMG: Compact Model for RF-SOI MOSFETs", accepted in IEEE Device Research Conference (DRC), Columbus, USA, June 2015.
- S. A. Ahsan, S. Ghosh, K. Sharma, A. Dasgupta, S. Khandelwal, and Y. S. Chauhan, "Capacitance Modeling of a GaN HEMT with Gate and Source Field Plates", accepted in IEEE International Symposium on Compound Semiconductors, Compound Semiconductor Week, June-July 2015.
- P. Rastogi, T. Dutta, S. Kumar, A. Agarwal, and Y. S. Chauhan, "First Principle Study of Quantization Effects on UTB InP MOSFET", accepted in IEEE International Symposium on Compound Semiconductors, Compound Semiconductor Week, June-July 2015.
- A. Dasgupta and Y. S. Chauhan, "Surface Potential Based Modeling of Induced Gate Thermal Noise for HEMTs", accepted in IEEE International Symposium on Compound Semiconductors, Compound Semiconductor Week, June-July 2015.
- S. Khandelwal, Y. S. Chauhan, B. Iniguez, and T. Fjeldly, "RF Large Signal Modeling of Gallium Nitride HEMTs with Surface-Potential Based ASM-HEMT Model", accepted in IEEE International Symposium on Compound Semiconductors, Compound Semiconductor Week, June-July 2015.
- A. Dasgupta, S. Ghosh, S. Khandelwal, and Y. S. Chauhan, "ASM-HEMT: Compact model for GaN HEMTs", accepted in IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC2015), Singapore, June 2015.
- K. Sharma, A. Dasgupta, S. Ghosh, S. A. Ahsan, S. Khandelwal, and Y. S. Chauhan, "Effect of Access Region and Field Plate on Capacitance behavior of GaN HEMT", accepted in IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC2015), Singapore, June 2015.
- H. Agarwal, C. Gupta, P. Kushwaha, C. Yadav, J. P. Duarte, S. Khandelwal, C. Hu, and Y. S. Chauhan, "Analytical Modeling and Experimental Validation of Threshold Voltage in BSIM6 MOSFET Model", accepted in IEEE Journal of Electron Devices Society, 2015.
- H. Agarwal, S. Khandelwal, S. Dey, C. Hu, and Y. S. Chauhan, "Analytical Modeling of Flicker Noise in Halo Implanted MOSFETs", appearing in IEEE Journal of Electron Devices Society, 2015.
- S. Khandelwal, J. P. Duarte, A. Medury, Y. S. Chauhan, and C. Hu, "New Industry Standard FinFET Compact Model for Future Technology Nodes", accepted in IEEE VLSI Technology symposium, Kyoto, June 2015.
- S. Khandelwal, H. Agarwal, J. P. Duarte, K. Chan, S. Dey, Y. S. Chauhan, and C. Hu, "Modeling STI Edge Parasitic Current for Accurate Circuit Simulations", accepted in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015.
- A. Dasgupta, S. Khandelwal, and Y. S. Chauhan, "Surface potential based Modeling of Thermal Noise for HEMT circuit simulation", appearing in IEEE Microwave and Wireless Components Letters, 2015.
- P. Kushwaha, N. Paydavosi, S. Khandelwal, C. Yadav, H. Agarwal, J. P. Duarte, C. Hu and, Y. S. Chauhan, "Modeling the Impact of Substrate Depletion in FDSOI MOSFETs", Solid State Electronics, Vol. 104, Issue 2, Feb. 2015.
- S. Ghosh, A. Dasgupta, S. Khandelwal, S. Agnihotri, and Y. S. Chauhan, "Surface-Potential-Based Compact Modeling of Gate Current in AlGaN/GaN HEMTs", IEEE Transactions on Electron Devices, Vol. 62, Issue 2, Feb. 2015
- P. Rastogi, S. Kumar, S. Bhowmick, A. Agarwal and, Y. S. Chauhan, "Doping Strategies for Monolayer MoS2 via Surface Adsorption: A Systematic Study", ACS Journal of Physical Chemistry C, Vol. 118, Dec. 2014.
- A. Dasgupta, S. Khandelwal, and Y. S. Chauhan, " Compact Modeling of Flicker Noise in HEMTs ", IEEE Journal of Electron Devices Society, Vol. 2, Issue 6, Nov. 2014.
- S. Ghosh, K. Sharma, S. Khandelwal, S. Agnihotri, T. A. Fjeldly, F. M. Yigletu, B. Iniguez, and Y. S. Chauhan, "Modeling of Temperature Effects in a Surface-Potential Based ASM-HEMT model", accepted in IEEE International Conference on Emerging Electronics (ICEE), Bangalore, India, Dec. 2014.
- P. Rastogi, S. Kumar, A. Agarwal, and Y. S. Chauhan, "Ab-initio study of doping versus adatom in monolayer MoS2", accepted in IEEE International Conference on Emerging Electronics (ICEE), Bangalore, India, Dec. 2014.
- A. Dasgupta, C. Yadav, P. Rastogi, A. Agarwal and Y. S. Chauhan, "Analysis and Modeling of Quantum Capacitance in III-V Transistors", accepted in IEEE International Conference on Emerging Electronics (ICEE), Bangalore, India, Dec. 2014.
- P. Kushwaha, C. Yadav, H. Agarwal, J. Srivatsava, S. Khandelwal, J. P. Duarte, C. Hu and Y. S. Chauhan, "BSIM-IMG with Improved Surface Potential Calculation Recipe", accepted in IEEE India Conference (INDICON), Pune, India, Dec. 2014.
- C. Yadav, P. Kushwaha, H. Agarwal, Y. S. Chauhan, "Threshold Voltage Modeling of GaN Based Normally-Off Tri-gate Transistor", accepted in IEEE India Conference (INDICON), Pune, India, Dec. 2014.
- H. Agarwal, Y. S. Chauhan, "Flicker Noise Modeling in BSIM6 Compact Model", MOS-AK Workshop, Venice, Italy, Sept. 2014.
- Y. S. Chauhan, "Compact Modeling of FinFET and Ultra-Thin-Body devices", INUP Workshop on Compact Modeling, Bangalore, August 2014.
- S. Khandelwal, J. P. Duarte, Y. S. Chauhan, and C. Hu, " Modeling 20nm Germanium FinFET with the Industry Standard FinFET Model ", IEEE Electron Device Letters, Vol. 35, Issue 7, July 2014.
- Y. S. Chauhan, P. Kushwaha, S. Khandelwal, C. Yadav, N. Paydavosi, J. P. Duarte and C. Hu, "BSIMIMG: COMPACT MODEL FOR UTBBSOI MOSFETs", Workshop on Compact Modeling, Washington D.C., USA, June 2014. (Invited)
- S. Khandelwal, J. P. Duarte, N. Paydavosi, Y. S. Chauhan, J. J. Gu, M. Si, P. D. Ye, and C. Hu, "InGaAs FinFET Modeling Using Industry Standard Compact Model BSIM-CMG", Workshop on Compact Modeling, Washington D.C., USA, June 2014.
- C. Yadav, P. Kushwaha, S. Khandelwal, J. P. Duarte, Y. S. Chauhan, and C. Hu, " Modeling of GaN based Normally-off FinFET ", IEEE Electron Device Letters, Vol. 35, Issue 6, June 2014.
- H. Agarwal, S. Khandelwal, Y. S. Chauhan, and C. Hu, "Noise Modeling in BSIM6 Compact Model", Workshop on Compact Modeling, Washington D.C., USA, June 2014.
- C. Yadav, S. Khandelwal, and Y. S. Chauhan, "Modeling of AlGaN/GaN FinFET", Workshop on Compact Modeling, Washington D.C., USA, June 2014.
- Y. S. Chauhan, "Semiconductor industry: CMOS technology and beyond", Motilal Nehru National Institute of Technology Allahabad, April 2014.
- Y. S. Chauhan, S. Venugopalan, M.-A. Chalkiadaki, M. A. Karim, H. Agarwal, S. Khandelwal, N. Paydavosi, J. P. Duarte, C. C. Enz, A. M. Niknejad and C. Hu, " BSIM6: Analog and RF Compact Model for Bulk MOSFET", IEEE Transactions on Electron Devices, Vol. 61, Issue 2, Feb. 2014. (Invited)
- A. Dutta, S. Sirohi, T. Ethirajan, H. Agarwal, Y. S. Chauhan, R. Q Williams, "BSIM6 - Benchmarking the Next Generation MOSFET Model for RF Applications", IEEE International Conference on VLSI Design, Mumbai, India, Jan. 2014.
- J. R. Sahoo, H. Agarwal, C. Yadav, P. Kushwah, S. Khandewal, R. Gillon, Y. S. Chauhan, "High Voltage LDMOSFET Modeling using BSIM6 as Intrinsic-MOS Model", IEEE PrimeAsia, Visakhapatnam, Dec. 2013. (Gold Leaf Certificate)
- S. Agnihotri, S. Ghosh, A. Dasgupta, S. Khandewal, Y. S. Chauhan, "A Surface Potential based Model for GaN HEMTs", IEEE PrimeAsia, Visakhapatnam, Dec. 2013. (Gold Leaf Certificate)
- S. Khandelwal, C. Yadav, S. Agnihotri, Y. S. Chauhan, A. Curutchet, T. Zimmer, J.-C. Dejaeger, N. Defrance and T. A. Fjeldly, "A Robust Surface-Potential-Based Compact Model for GaN HEMT IC Design", IEEE Transactions on Electron Devices, Vol. 60, Issue 10, Oct. 2013.
- N. Paydavosi, S. Venugopalan, Y. S. Chauhan, J. P. Duarte, S. Jandhyala, A. M. Niknejad and C. Hu, "BSIM - SPICE Models Enable FinFET and UTB IC Designs", IEEE Access, 2013.
- H. Agarwal, S. Venugopalan, M. Chalkiadaki, N. Paydavosi, J. P. Duarte, S. Agnihotri, C. Yadav, P. Kushwaha, Y. S. Chauhan, C. C. Enz, A. Niknejad and C. Hu, "Recent Enhancements in BSIM6 Bulk MOSFET Model", IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Glasgow, Scotland, Sept. 2013.
- Y. S. Chauhan, S. Venugopalan, N. Paydavosi, P. Kushwaha, S. Jandhyala, J. P. Duarte, S. Agnihotri, C. Yadav, H. Agarwal, A. Niknejad and C. Hu, "BSIM Compact MOSFET Models for SPICE Simulation", IEEE International Conference Mixed Design of Integrated Circuits and Systems (MIXDES), Gdynia, Poland, June 2013. (Invited)
- Y. S. Chauhan, "Industry Standard SPICE Modeling", Solid State Physics Laboratory (SSPL) - DRDO, Delhi, June 2013.
- S. Khandelwal, S. Sharma, Y. S. Chauhan, T. Gneiting and T. A. Fjeldly, "Modeling and Simulation Methodology for SOA Aware Circuit Design in DC and Pulsed-Mode Operation of HV MOSFETs", IEEE Transactions on Electron Devices, Vol. 60, Issue 2, Feb. 2013.
- Y. S. Chauhan, M. Chalkiadaki, S. Venugopalan, M. A. Karim, N. Paydavosi, S. Jandhyala, J. P. Duarte, C. Enz, A. Niknejad, C. Hu, "Global Geometrical Scaling in BSIM6", MOS-AK Workshop, San Francisco, Dec. 2012.
- S. Khandelwal, Y. S. Chauhan, T. A. Fjeldly, "Analytical Modeling of Surface-Potential and Intrinsic Charges in AlGaN/GaN HEMT Devices", IEEE Transactions on Electron Devices, Vol 59, Issue 8, Oct. 2012.
- Y. S. Chauhan, R. Gillon, M. Declercq, A. M. Ionescu, "Impact of Lateral Nonuniform Doping and Hot Carrier Injection on Capacitance Behavior of High Voltage MOSFETs", IETE Technical Review, Vol. 25, Issue 5, pp. 244-250, Sept.-Oct 2008.
- M. A. Karim, Y. S. Chauhan, S. Venugopalan, A. B. Sachid, D. D. Lu, B.-Y. Nguyen, O. Faynot, A. M. Niknejad and C. C. Hu, "Extraction of Isothermal Condition and Thermal Network in UTBB SOI MOSFETs", IEEE Electron Device Letters, Vol. 33, No. 9, Sept. 2012.
- M.-A. Chalkiadaki, A. Mangla, C. C. Enz, Y. S. Chauhan, M. A. Karim, S. Venugopalan, A. Niknejad, C. Hu, "Evaluation of the BSIM6 Compact MOSFET Modelʹs Scalability in 40nm CMOS Technology", IEEE European Solid-State Device Research Conference, Bordeaux, France, Sept. 2012.
- Y. S. Chauhan, S. Venugopalan, M. A. Karim, S. Khandelwal, N. Paydavosi, P. Thakur, A. M. Niknejad and C. C. Hu, "BSIM - Industry Standard Compact MOSFET Models", IEEE European Solid-State Device Research Conference, Bordeaux, France, Sept. 2012. (Invited)
- Y. S. Chauhan, M. A. Karim, A. Niknejad, C. Hu, "Thermal Network Extraction in Ultra-Thin-Body SOI MOSFETs", MOS-AK Workshop, Bordeaux, France, Sept. 2012.
- S. Khandelwal, Y. S. Chauhan, D. D. Lu, S. Venugopalan, M. A. Karim, A. B. Sachid, B.-Y. Nguyen, O. Rozeau, O. Faynot, A. M. Niknejad and C. C. Hu, "BSIM-IMG: A Compact Model for Ultra-Thin Body SOI MOSFETs with Back-Gate Control", IEEE Transactions on Electron Devices, Vol. 59, Issue 8, pp. 2019-2026, Aug. 2012
Dr. Yogesh Singh Chauhan
- Sudip Ghosh
- Tapas Dutta
- Chandan Yadav
- Pragya Kushwaha
- Shantanu Agnihotri
- Harshit Agarwal
- Priyank Rastogi
- Sheikh Aamir Ahsan
- Avirup Dasgupta
- Girish pahwa
- Chetan Gupta
- Prateek Jain
- Dinesh R
- K.L.N. Acharya (Visiting Researcher)
- Piyush Kumar
- Noor Mohamed E V
- Jayadeepthi B
- Mahendra Jalkhediya
- Kurnikamarthi Omprakash
- Rajender Nune
- Boyina Sri Syamalaraju
- Shalini Dey
- Yogendra Sahu
- Rahul Agrawal
- Mayank Agarwal
- Shivendra Singh Parihar
- Chetan Kumar Dabhi
Mr. Mukesh Rawat
Ph: 0512-679-7257
Location: WL 215